This invention relates to circuits and methods for sampling the level of a signal and holding the sampled value constant for a predetermined period of time, and particularly to circuits and methods which provide a high slew rate during sample acquisition and a stable hold output.
Sample and hold circuits typically employ a switching device for periodically connecting a capacitor to an input signal to be sampled so that while the capacitor is connected to the signal it will charge or discharge to the voltage level of the signal, and after the switch is disconnected the capacitor will hold that voltage level. The capacitor is also typically connected to a high impedance input of a buffer amplifier which provides the hold output signal of the sample and hold circuit, the high impedance input ensuring minimal discharge of the capacitor during the hold phase of the circuit's operation.
Where the signal to be sampled is derived from a relatively high impedance source an input amplifier to the sample and hold circuit is also typically employed preceding the switching device to provide a relatively low impedance source of current to the charging capacitor thereby minimizing the time required for the capacitor to charge or discharge from one voltage level to another. Nevertheless, the time required for the capacitor to charge or discharge from one voltage level to another, that is the "acquisition time" of the sample and hold circuit, is limited by, among other things, the finite effective source impedance from which the charging signal is derived. As the frequency of the sample signal and, hence, the sampling rate increase, the acquisition time takes on greater significance.
One of the applications for sample and hold circuits is to eliminate certain defects in the output of a typical digital-to-analog converter ("DAC"). Due to the nature of operation of a DAC and to practical limitations in the construction of a theoretically perfect DAC, the analog output of a DAC typically includes spikes, or "glitches", occurring during conversion events, i.e., the transition of the output from one voltage level to another. Although the high frequency components in the analog output of a DAC resulting from the conversion switching frequency can be eliminated by low pass filtering, the glitches introduce frequency components that often lie within the spectrum of the analog signal to be reconstructed and therefore produce significant distortion in some applications. Consequently it is desirable to eliminate those glitches.
One approach to the elimination of glitches in the output of a DAC is to employ a sample and hold circuit at the output of the DAC, commonly known as a "deglitcher". The output of the DAC settles to within an acceptable accuracy of the new voltage level within a maximum settling time following the beginning of the conversion event. In the use of a sample and hold circuit as a deglitcher the output of the DAC is sampled after the settling time of one event has passed and held until the settling time of the next event has passed, and so on. Thus, the output of the sample and hold circuit is held during the time that the glitches occur, thereby eliminating their effect, though introducing a slight output time delay. An example of a circuit that employs such a method is found in the GVG 3280, Four Channel Audio Multiplex system manufactured and sold by the Grass Valley Group of Tektronix, Inc.
While a deglitcher of the type previously described eliminates the frequency components otherwise introduced by glitches, the resultant signal is still not a perfect "stair-step" output, due to the acquisition time of the sample and hold circuit. Heretofore efforts to increase the slew rate of sample and hold circuits, and thereby decrease acquisition time, have compromised hold stability, and vice versa. This is because, in part, acquisition time increases as the size of the storage capacitor increases and hold stability, or "droop," increases as the size of the storage capacitor decreases. The distortion introduced by aquisition droop is in many cases significant and introduces frequency components that cannot be eliminated by low pass filtering.
Accordingly, it would be desirable to have a sample and hold circuit which minimizes the need to trade off hold stability for high slew rate, and which could be employed to deglitch the output of a DAC while introducing minimal additional distortion.